The demand for smaller, more portable electronic products with increased functionality has been fueling growth in many markets and applications. To provide these products, designers have been turning to reduced size packing methods such chip scale packages (CSPs). One particular implementation of CSPs, wafer CSPs (WCSPs), allows the package size to be reduced to the size of the die itself and eliminates the need for the larger interposer layer typical of larger CSPs.
WCSP eliminates conventional packaging steps such as die bonding, wire bonding, and die level flip chip attach processes to a package substrate by using the IC die itself as the WCSP substrate. Use of the die itself as the WCSP substrate significantly reduces the footprint to the IC die itself as compared to the same IC die attached to a larger footprint package substrate (e.g., PCB substrate).
WCSP can be embodied as direct-bump WCSP or redirect layer (RDL) WCSP which unlike direct-bump WCSP adds a RDL that functions as a rewiring layer to enable repositioning of the external input/output (I/O) terminals at desired positions. In a typical RDL WCSP production flow, after completion of conventional back end of the line (BEOL) wafer fab processing, the WCSP die generally includes die pads (also known as bond pads) and a dielectric passivation layer over the BEOL metal stack, except for passivation openings over the die pads. A first WCSP dielectric (e.g., a polyimide) is deposited. Lithography/etch forms first dielectric vias in the first WCSP dielectric over the die pads, followed by deposition and patterning of an RDL metal including a plurality of RDL traces which contact the die pads and extends laterally therefrom to RDL capture pads. A second WCSP dielectric (e.g., a polyimide) is then deposited and second dielectric vias formed that reach the RDL in RDL capture pad positions that are lateral to the position of the die pads. The first and second dielectric vias are both conventionally circular, or in some case square, in cross-sectional shape.
Under bump metallization (UBM) pads commonly referred to as “ball pads” or “bump pads” are formed over the second dielectric vias and are coupled to and generally enclosed by the RDL capture pads, followed by forming metal (e.g., solder) balls, pillars or other bonding connectors on the UBM pads. Each bonding connector, such as a solder ball, provides a repositioned external I/O connection for the WCSP die. The WCSP wafer is then singulated to form a plurality of singulated WCSP die, commonly for use on boards for portable devices where the board area is valuable.
One challenge for WCSP devices is reliability. Typically, board-level reliability (BLR) tests include temperature cycling (TC), drop, and bend testing. For BLR-TC, WCSPs are conventionally mounted onto organic printed circuit boards and subjected to TC, and the properties of the RDL and the solder balls, as well as the properties of any adhesion or diffusion barrier layers used therebetween, are evaluated. As the WCSP die size increases, the reliability which may be evidenced in an accelerated fashion during BLR-TC testing is known to decrease. BLR-TC performance for WCSP die has been conventionally addressed by implementing changes to the WCSP process and materials (e.g., alternative dielectrics), which have somewhat improved BLR-TC performance.